Graph-IC Verification
نویسنده
چکیده
In this paper, we describe the application of graph-based verification techniques to a complex and highly configurable display controller IP block. The main challenges, the technology and the major benefits are developed, including the reuse at system level for basic connectivity verification and more complex system-level tests involving multiple IPs.
منابع مشابه
3D-IC System Verification Methodology: Solutions and Challenges
A verification methodology for 3D-ICs is presented, including connectivity checking and parasitic extraction. An example was given to illustrate a true 3D-IC stack verification using a GDS based flow. The new challenges were presented and the development efforts to respond to those challenges were identified.
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